1. Field of the Invention
Embodiments of the present invention relate generally to microelectronic packaging, and, more specifically, to multi-chip or system-in-package modules with semiconductor devices in a stacked arrangement.
2. Description of the Related Art
Packaging of electrical circuits is a key element in the technological development of any device containing electrical components. Integrated circuits are typically fabricated on a semiconductor wafer which may be diced to form a semiconductor die or chip. The die or chip may then be coupled to a substrate to form a package. Some packages may include multiple semiconductor dies coupled to a substrate to form Multi-Chip Module (MCM) devices. Certain MCM packages may include a processor, such that the package forms a mini-system. These self-contained mini-systems are commonly referred to as System-in-Package (SIP). SIP or MCM devices are commonly used in small electronic devices such as cell phones, digital music players, personal organizers, etc. One mechanism for increasing the amount of electrical circuitry in the package, without increasing the surface mount space necessary to house the components, is to stack the chips or dies on top of each other in a vertical fashion. The final step in formation of a SIP is to provide external interconnects to and/or encapsulate the stacked components.
Although the stacked arrangement in SIP and MCM devices minimizes the amount of surface area or “real estate” needed as compared to horizontally oriented packages, the stacked arrangement also introduces new challenges. The reduced surface area limits the horizontal placement of semiconductor dies and chips, and components that might not lend themselves to a stacked arrangement may be forced into a suboptimal location or orientation. Proper location and orientation are typically desirable to insure electrical conductivity between components and to reduce or eliminate any electrical interference. There are increasing difficulties in electrically connecting the various components to the substrate and each other because of the forced locations and orientations of the components due to the reduced surface area. For example, such components commonly use bond pads, in which the bond pads of one component are connected to a substrate or another component through the use of bond wires. The connectivity of the bond pads is limited by the space available on the mounting surface, and the bond pads of one component may not overlie the bond pads of another component or the contact pads of a substrate.
Other types of electronic connecting techniques, such as Fine-Pitch Ball Grid Array (FPGA) or Ball Grid Array (BGA) technology, may suffer similar problems. BGA packages implement conductive metal, such as solder, which is formed into spheres or balls and disposed on conductive ball pads on a substrate or other surface. The solder balls are generally configured into an array to provide mechanical as well as electrical interfaces between components and a substrate.
Additional challenges in designing SIP devices include the lack of vertical space between components and placement of components that may not lend themselves to embedding in a vertical stack. For example, vertical integration of components may lead to problems with encapsulating the package with a molding compound, resulting in air pockets and voids that may lead to conductivity gaps. Some components that may be required by the package, such as filter capacitors, may be limited to surface mounting and cannot be embedded elsewhere in the SIP or MCM stack, further complicating the space and connectivity issues.